The present invention relates generally to memory devices and in particular the present invention relates to a memory with row redundancy and its operation.
Memory devices are typically provided as internal storage areas in a computer. One type of memory used to store data in a computer is random access memory (RAM). RAM is typically used as main memory in a computer environment. Most RAM is volatile. That is, RAM generally requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, all data stored in the RAM is lost.
Another type of memory is a non-volatile memory. A non-volatile memory is a type of memory that retains stored data when power is turned off. A flash memory is a type of non-volatile memory. An important feature of a flash memory is that it can be erased in blocks instead of one byte at a time. Each block of memory in a memory array of the flash memory comprises rows and columns of memory cells. Many modern computers have their basic I/O system (BIOS) stored on flash memory chips.
As with other memory devices, defects can occur during the manufacture of a flash memory array having rows and columns of memory cells. Typical defects can include bad memory cells, open circuits, shorts between a pair of rows and shorts between a row and column. Shorts typically occur because of the large number of rows and columns of memory cells that have to be placed in close proximity to each other on an integrated circuit. Defects can reduce the yield of the flash memory device. A way to resolve this problem, without discarding the memory device, is to incorporate redundant elements in the memory that selectively replace defective elements. For example, redundant rows are a common form of redundant elements used in flash memory to replace a defective primary row. Redundant columns are another common form of redundant elements used in flash memory to replace a defective primary column.
After a memory die has been manufactured, it is tested for defects. Generally with volatile memory, redundancy circuitry is used to selectively route access requests directed to the defected elements to the redundant elements. Redundancy circuitry can comprise electrical fuses that are selectively xe2x80x9cblownxe2x80x9d (i.e. open circuited) to disconnect the shorted rows. The redundant rows are then activated to replace the shorted rows. The electrical fuses are generally blown by one of two methods. The first is known as the Ohm heating method. This method involves driving a substantial current through a fuse to melt the fuse""s conductive material. The other method is known as the laser method. The laser method uses a laser to cut a fuse""s conductive material. Anti-fuse circuitry can also be used. Anti-fuses are normally open and short-circuited (closed) when programmed.
Some memory devices, including some flash memory devices, utilize non-volatile registers to store addresses of primary elements that are designated to be replaced. The addresses of the primary elements are stored in the registers by the manufacturer. The registers are generally coupled to a redundant circuit. The redundant circuit compares address requests to addresses stored in the registers. If an address request matches an address stored in a register, the redundant circuit directs or maps the access request to the redundant row instead of the shorted row.
Generally, the use of redundant elements work well, however, problems can occur if the defect involves shorts between two rows or shorts between a row and a column in the primary array. This is because, even though a redundant row or column is read to or written to instead of the shorted row or column, the short is still embedded in the primary memory array and the defect can effect other elements in the primary memory array. One problem generally arises during pre-program and soft program cycles of an erase operation. An erase operation is an algorithm that typically comprises a pre-programmed cycle, an erase cycle and a soft program cycle. The pre-programmed cycle of an erase operation puts each memory cell in a programmed state by applying a program pulse to each row of memory cells. The soft program cycle or heal cycle corrects any over-erased memory cells after the erase cycle has been completed by applying a soft program pulse to the over-erased memory cells.
Disabling the redundancy circuit during the pre-program and soft program cycle when a row or column is addressed that is shorted to another row is one method of dealing with this problem. This allows the pre-program and soft program cycle to be applied to the shorted rows and columns in the primary memory array. By doing this, the effect of the shorts on other elements in the primary memory array is eliminated or at least minimized.
However, a problem arises when dealing with a row to row short. When a first row is addressed that is shorted to a second row and a pre-program pulse of a preprogram cycle is applied or a soft program pulse of a soft program cycle is applied, the second row also receives the respective pre-program pulse or soft program pulse. This creates a conflict between a driver of the first shorted row and the driver of the second shorted row that could lead to a collapse of the voltage supply that is driving the rows. If this were to happen, the memory cells in the first and second rows may not get properly programmed. A method of dealing with this problem is by activating the first row and the second row and simultaneously applying the respective pre-program cycle or soft program cycle to the rows. This in turn, creates another problem when the address is incremented after the respective pre-program cycle or soft program cycle has been completed because the next address will be the second shorted row. A way to skip over the second row is needed or another pre-program cycle or soft program cycle will be applied to the first and second shorted rows. This could potentially place too much charge on the memory cells of the rows.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a flash memory that has the ability to reduce exposure of programming voltages to rows shorted together.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a flash memory device includes a memory array, a state machine and a defect register. The state machine is used to control operations to the memory array. The defect register is used to store data indicating a type of defect. The state machine then increments row addresses during an erase operation based on the type of defect stored in the defect register.
In another embodiment, a flash memory device includes a memory array having memory cells arranged in rows and columns, control circuitry, at least one register and a logic circuit. The control circuitry is used to control memory operations. The at least one register is used to store an error code. The logic circuit selectively signals the state machine when a register is accessed during an erase operation that has an error code that indicates a row to row short. Thereafter, the state machine increments row addresses such that only one of two rows shorted together is addressed during a program cycle.
In another embodiment, a flash memory device includes a memory array, a state machine and a logic circuit. The memory array has primary columns and primary rows of memory cells. The memory array further has redundant rows. The state machine controls memory operations. The logic circuit signals the state machine when a row in the primary array is addressed during a program cycle of an erase operation that is shorted to another row in the primary array. Thereafter, the state machine increments row addresses such that only one of the two rows shorted together is addressed during the program cycle.
In another embodiment, a flash memory device includes a memory array, a redundancy circuit, a logic circuit and control circuitry. The memory array has memory cells arranged in primary rows and primary columns. The memory array further has multiple redundant rows that are used to selectively replace defective primary rows. A register is used for each redundant row to store an address of an associated defective primary row and an error code that indicates a type of defect in the associated defective primary row. The redundancy circuit is used to compare address requests to addresses stored in the registers and to decode the error codes. The redundancy circuit redirects address requests from defective primary rows to the redundant rows when an address request matches an address in a register. The logic circuit is coupled to the redundancy circuit and is used to generate a signal in response to an error code in a register that indicates a primary row shorted to another primary row has been addressed. The control circuitry is used to control memory operations to the memory array. When the control circuitry receives the signal from the logic circuit, the control circuitry disables the redundancy circuit during a pre-program or soft program cycle of an erase operation. The control circuitry further activates the primary rows shorted together and applies the respective pre-program or soft program cycle to the rows simultaneously and then increments the row address past the addresses of the shorted primary rows.
In another embodiment, a flash memory device includes a memory array, at least one redundant element, a register, a redundancy circuit, a state machine and a logic circuit. The memory array has a primary array of memory cells arranged in rows and columns. The at least one redundant element is used to selectively replace an associated defective element in the primary array. Each redundant element is used to store an address of the associated defective element and an error code that indicates the type of defect in the defective element. The redundancy circuit compares address requests with addresses stored in the registers and to decode the error code in the associated register. The redundancy circuit redirects address requests from the defective element to the redundant element when an address is matched. A state machine is used to control memory operations. The state machine disables the redundancy circuit during a program cycle of an erase operation when the redundancy circuit matches an address request to an address in a register and the error code in the register indicates a row to row short. The logic circuit is coupled to the redundancy circuit and is used to supply a signal to the state machine in response to an error code indicating a row to row short. The state machine increments row addresses such that only one of two rows shorted together is addressed during a program cycle in response to receiving the signal from the logic circuit.
In another embodiment, a flash memory system includes a processor to provide data, a memory array arranged in rows and columns to store the data, at least one redundant row, a register for each redundant row, a redundancy circuit, a logic circuit and control circuitry. The at least one redundant row is used to selectively replace an associated defective row in the memory array. Each register is used to store an address of an associated defective row in the memory array and an error code that indicates the type of error the redundant row is used to correct. The redundancy circuit is used to compare row address requests to redundancy row addresses and redirect address requests from the defective row to the redundant row. The logic circuit to generate a signal when the redundancy circuit matches an address request to an address in a register during a program cycle and the error code in the register indicates a row has been addressed that has a row to row short. The control circuitry is used to control memory operations. The control circuitry disables the redundancy circuit from redirecting address requests when the signal is received from the logic circuit. The control circuitry further directs an address counter to increment the row address past the rows shorted together upon completion of the program cycle on the rows shorted together.
A method of operating a flash memory system comprises performing a program cycle on a memory array having memory cells arranged in rows and columns, signaling a state machine when a row shorted to another row has been addressed, activating rows shorted together, applying program pulses to memory cells coupled to the shorted rows simultaneously and incrementing a row address beyond the rows shorted together upon completion of the program cycle on the shorted rows.
Another method of operating a flash memory system comprises performing a program cycle on a memory array having memory cells arranged in rows and columns, signaling a state machine when a row shorted to another row has been addressed, activating rows shorted together, applying program pulses to memory cells coupled to the shorted rows simultaneously and incrementing a row address beyond the rows shorted together upon completion of the program cycle on the shorted rows.
Another method of operating a memory system comprises performing a pre-program or soft program cycle on a memory array, producing a signal that is recognized by a state machine when a row is addressed that is shorted to another row, applying the respective pre-program or soft program cycle on the rows shorted together simultaneously and incrementing the row address so that the respective pre-program or soft program cycle is only applied once simultaneously to the rows shorted together.
A method of operating a flash memory during a pre-program cycle comprises applying a pre-program pulse to rows in a memory array incrementally until a row address matches an address in a register and an error code in the register indicates the row at that address is shorted to another row, activating the rows shorted together, applying a pre-program pulse to memory cells coupled to the rows shorted together simultaneously as the columns are incremented, incrementing the row address past the rows shorted together and applying a pre-program pulse to remaining rows in the memory array incrementally.
A method of operating a flash memory during a soft-program cycle comprises monitoring each column for a current level that would indicate a memory cell is coupled to the column that is over-erased, when a column is discovered that has a current level that would indicate an over-erased cell is coupled to the column, applying a soft program pulse to rows coupled to the column incrementally until the current level no longer indicates an over-erased memory cell is coupled to the column or a row address matches an address in a register and an error code in the register indicates the row is shorted to another row, when a row is address that is shorted to another row, activating the shorted rows, applying a soft program pulse to cells coupled to the rows shorted together simultaneously, verifying if a current level in the column still indicates a memory cell is coupled to the column, when a current level still indicates a memory cell is coupled to the column, incrementing the row address past the rows shorted together and applying a soft program pulse to remaining rows in the memory array until the current level no longer indicates an over-erased memory cell is coupled to the column.
Another method of operating a flash memory system comprises applying a program cycle to rows in a memory array incrementally until a row address matches a redundancy row address stored in a register, reading an error code in the register indicating the row addressed is shorted to another row, disabling the redundancy circuit from redirecting the address request to a redundancy row, activating the current row and the following row simultaneously, applying the program cycle to the shorted rows simultaneously, sending an enable signal from a redundancy circuit to a logic circuit indicating the error code was row to row short, sending a jump row signal from the logic circuit to a state machine during the program cycle on the shorted rows, incrementing the row address beyond the shorted rows, wherein the state machine increments the row address based on the jump row signal sent by the logic circuit after the program cycle has been completed on the shorted rows and applying the program cycle to remaining rows in the memory array incrementally.
A method of operating a flash memory system having a memory array with a row N shorted to a row N+1 comprises performing a pre-program or heal program cycle of an erase operation on rows of the memory array incrementally, addressing row N, signaling a state machine that row N is shorted to row N+1, activating row N and row N+1, applying a pre-program or heal program cycle to row N and row N+1 simultaneously, incrementing the row address twice after the pre-program or heal program cycle has been completed on row N and row N+1 and before the pre-program or heal program cycle is applied on a following row and performing a pre-program or heal program cycle of an erase operation on the remaining rows of the memory array incrementally.
A method of operating a memory system having a memory array with a row (row N) shorted to another row (row N+1) during a pre-program or soft program cycle comprises addressing row N, reading an error code stored in a register that indicates row N is shorted to row N+1 with a redundancy circuit, disabling the redundancy circuit from pointing the address request from row N to a redundant row, activating row N and row N+1, performing the pre-program or soft program cycle on row N and row N+1 at the same time and incrementing an address counter to row N+2.